
Senior Mask Design Engineer - Hardware
Role involves physical/custom layout and floorplanning for mixed-signal functions (PLLs, SerDes, ADCs, ESD) in submicron CMOS, working with ASIC and mixed-signal engineers. Requires deep Cadence Virtuoso expertise, experience with verification tools (Dracula, Hercules, Calibre, PrimeYield), DRC/LVS flows, and scripting (Perl, Python, SKILL). Position is hybrid and based in the US (Santa Clara referenced).













