
Senior LPU ASIC Engineer
NVIDIA is hiring a Senior LPU ASIC Engineer to own block/partition and top-level physical design (synthesis, P&R, CTS, routing, extraction, verification), drive low-power and PPA optimizations, integrate high-speed IP (SerDes/PCIe/CXL), develop automated EDA flows, and lead tapeout/sign-off activities. Requires 5+ years of relevant industry experience and expertise in UPF/LEC, MCMM STA, EDA tools, and scripting (TCL/Python/Perl).















