Hands-on architect/engineer position responsible for operationalizing GPU computing products and software stacks, providing at-scale system analysis and tuning for large GPU-accelerated datacenter/HPC deployments. Requires 8+ years of experience with accelerated computing, programming/scripting (C/C++, Python, Bash), parallel filesystems, and strong system administration and communication skills.

Role involves partnering with NVIDIA engineering, product, and sales to secure design wins; performing proof-of-concepts and in-depth profiling/optimization of ML/DL models on GPU architectures; working with client ML researchers and engineers; and producing collateral (notebooks, blogs) for finance use-cases. Requires 12+ years of relevant experience and strong Python/C++ and ML/DL framework knowledge.

NVIDIA seeks a Senior CPU Design Engineer to drive micro-architecture definition, implement RTL (Verilog/SystemVerilog), collaborate with verification and physical design teams, and meet performance, timing and power targets. Requires BS/MS in EE/CE (or equivalent) and 8+ years of experience in micro-architecture and RTL development of high-speed CPU-related designs; proficiency in logic design, physical design/VLSI, and scripting (Python/Perl).

Work on GPU communications libraries (e.g., NCCL, NVSHMEM, UCX) to improve communication performance for large-scale Deep Learning and HPC systems. Responsibilities include co-designing HW/SW solutions, building proofs-of-concept, running experiments and simulations, and performance modeling. Requires M.S./Ph.D. or equivalent, 5+ years experience, strong C/C++, parallel programming/runtime experience, Linux, and deep understanding of system and network architecture.

NVIDIA seeks a Senior System Software Engineer to design, develop, test, and optimize system software for next-generation ARM-based SoCs and datacenter products. Requires 6+ years of relevant experience in computer architecture or software development, strong skills in OS internals, multicore systems, performance analysis (including linux perf), device drivers, and performance optimization; familiarity with CUDA and HPC is a plus.

Lead architecture and implementation of next-generation fleet management and telemetry solutions for large-scale GPU/Grace-based infrastructure. Requires hands-on coding in C/C++ and Python, experience with time-series databases (InfluxDB, Prometheus), telemetry visualization (Grafana), firmware architecture, REST APIs (Redfish a plus), and proven scalability engineering experience.

Design and implement digital and mixed-signal circuit IPs for voltage and noise sensing, perform detailed transistor-level analysis (SPICE, EM/IR, timing) and prototype ideas on test chips. Requires BSEE (MS preferred) and 8+ years of relevant experience; role includes mentoring junior engineers and cross-functional collaboration.

Work on design and implementation of GPU-accelerated libraries and SDKs for unstructured sparsity in deep learning and HPC. Responsibilities include developing a C++ system for sparse tensor computations, DSL specifications for sparse storage formats, on-demand code generation, enabling frameworks like Python/PyTorch, and performance evaluation and optimization. Required: BS/MS/PhD (or equivalent), 6+ years developing and optimizing high-performance C++ software, strong Python and CUDA skills, and experience with parallel programming (MPI/OpenMP) and sparse compilers (MLIR or TACO).

NVIDIA seeks a Solutions Architect for its AI Software Segment to develop end-to-end AI solutions, support LLMs and multimodal models, and guide customers through data processing, training, evaluation, RL, and model optimization. Requires 5+ years with AI frameworks (PyTorch, JAX, TensorFlow), Python, Linux, experience with distributed training tools (Kubernetes, SLURM), and expertise in GPU-based model training. Location noted as US (remote) and Santa Clara; salary range stated.

Work on GPU-accelerating high-performance database and ETL applications: analyze and optimize data-intensive workloads, collaborate with hardware/software teams to influence future architectures and programming models. Requires a Master's/PhD or equivalent, 5+ years' relevant experience, strong C/C++ and low-level parallel programming (CUDA, OpenMP, MPI, etc.), and expertise in CPU/GPU architecture and memory subsystems.

Work on DGXC Data Services to design, implement, and operate scalable cloud-native data and storage services (discovery, ingestion, governance, checkpointing, observability, low-latency access) for exabyte-scale, high-performance GPU training and inference. Requires ~5+ years software engineering experience and hands-on experience with Kubernetes, public cloud providers (AWS/GCP/Azure), backend languages (e.g., Go, Python, Rust, C++, Java), distributed systems, and production reliability.

NVIDIA seeks a Distinguished Engineer to lead architecture, systems, and software strategy for AI-native wireless infrastructure (RAN and core), drive GPU-accelerated prototyping, and engage with industry standards (3GPP, O-RAN) and partners. The role requires 20+ years of industry experience and deep expertise in communications theory, RAN (5G NR) PHY/L1/L2, baseband signal processing, AI/ML, and programming in Python, C/C++, and Matlab. Salary range provided: 320,000–488,750 USD/year.

Lead the creation and validation of scalable datacenter and cluster designs for enterprise AI/ML, focusing on networking, compute, storage and cloud-native integration. Requires 8+ years in hardware or infrastructure architecture, expertise in datacenter networking (Ethernet, InfiniBand, LAN/WAN, SDN), cluster design, cloud-native patterns and TCO analysis. Position is remote within the US.

Design, implement, and optimize scalable high-performance sparse linear algebra software for GPU architectures (sparse BLAS, direct and iterative solvers, preconditioners, AMG). Collaborate with library engineers, QA, product management, and external partners. PhD/MSc preferred; 5+ years of relevant experience in C++ and parallel programming technologies (CUDA, MPI, OpenMP, OpenACC, pthreads). Salary ranges provided in posting.

NVIDIA is hiring a Senior Systems Software Security Engineer to design, implement, and deliver security features for Data Center systems — including root of trust, secure boot, attestation, firmware, and management interfaces — using industry standards (OpenBMC, UEFI, SPDM, PLDM, Redfish, NIST SP800-193, CNSA2.0). Requires a BS/MS (or equivalent), 5+ years of software/firmware security engineering experience, Python and system programming skills, and experience with enterprise server delivery.

Work on JAX core design and performance optimizations for NVIDIA products, collaborating with AI researchers and cross-functional teams. Requires BS or equivalent and 6+ years' relevant experience, proficiency in C/C++ and Python, familiarity with ML frameworks (e.g., PyTorch, TensorFlow), and strong knowledge of CPU/GPU architectures and distributed training. Base salary ranges provided: 184,000–356,500 USD/year depending on level.

Role to serve as the technical voice for NVIDIA GPU and rack-scale systems, translating GPU and system design (NVL72, NVLink, CPU/GPU co-design, power delivery, liquid cooling) into technical content and customer-facing materials. Requires 7+ years of relevant experience and BS/MS or equivalent, with deep expertise in GPU architecture, accelerators, and data center system components.

Seeking a senior, highly technical Developer Relations Manager to consult with developers and partners on integrating NVIDIA’s Physical AI, Generative AI, and World Foundation Models. Role requires deep hands-on experience with LLMs/VLMs, model optimization (quantization, inference techniques), developer program leadership, and working with NVIDIA platforms (Omniverse, Cosmos, Isaac). Minimum ~8 years industry experience with 5+ years in relevant hands-on AI/Physical AI work is required.

Lead developer relations efforts for agriscience verticals (seeds/traits, crop protection, plant nutrition, digital agronomy). Responsibilities include technical advising, enablement (sample code, demos, pipelines), partner onboarding and integration, mapping and growing the developer ecosystem, and collaborating with solution architects, engineering, product and marketing. Requires a Master’s/PhD or equivalent and a minimum of 8+ years in agriscience-related roles with 5+ years hands-on domain experience.

Seeking a Senior Mask Layout Design Engineer with 7+ years' experience performing physical layout for mixed-signal functions (PLLs, high-speed SerDes, ADCs, ESD) in submicron CMOS technologies. Must be experienced with Cadence Virtuoso, verification tools (Calibre, PrimeYield, Dracula, Hercules), DRC/LVS flows, and scripting (Perl, Python, Skill). Location indicated as US (Santa Clara) and remote options.