
Senior ASIC Design Verification Engineer - LPU
NVIDIA is hiring a Senior ASIC Design Verification Engineer to verify design and implementation of inference accelerator ASICs, develop verification infrastructure and automated flows, and collaborate with architects, designers, and pre/post-silicon teams. Requires a BS in EE/CS/CE (or equivalent) with 8+ years' relevant experience and strong skills in SystemVerilog, UVM, verification tools (e.g., VCS/Verdi), scripting (Perl/Python/C/C++), and knowledge of the ASIC design flow.